High Speed Convolution Using Residue Number Systems

This thesis investigates architectures for high speed signal convolution using residue number system techniques. The focus is on VLSI implementations, a choice that gives two parameters by which judge different architectures: speed and hardware size. Although the focus is on the standard residue number system, the same concepts can be directly applied to quadratic residue number system architectures as well. Two general design classes are developed with several detailed implemetations investigated in each class. Using the size and speed results of the detailed designs, a design aid was developed that prunes the design space leaving a core group of designs with optimal speed/size combinations. One of the largest disadvantages of residue number system implementations of computational hardware is the large overhead associated with the conversion into and out of residue representation. To provide a comparision between residue number system architectures and conventional binary architectures a design is presented that uses several of the design optimizations developed for the residue designs. Thesis Supervisor: Bruce R. Musicus Title: Assistant Professor of Electrical Engineering a